1. Field of the Invention
The present invention relates to a semiconductor memory device and a semiconductor memory element, in particularly, to a non-volatile semiconductor device and a non-volatile semiconductor element.
2. Description of the Related Art
Non-volatile memories are used in various applications, such as storing data of an IC card or the like and tuning of an analog circuit. A memory capacity necessary for such a non-volatile memory is not large; several kilobits to several hundreds of kilobits are sufficient for data storage, and several tens of bits are sufficient for tuning. If a non-volatile memory having such a small memory capacity can be manufactured by a general CMOS process, a CMOS and a non-volatile memory can be mounted together in a single chip without increasing the number of manufacturing steps, and hence the cost can be kept low.
Japanese Patent Publication No. 2005-533372 discloses a non-volatile semiconductor device formed by a CMOS process. In this Patent Application, a P-channel MOS transistor having a floating gate is used as a non-volatile semiconductor element, and electrons are injected into the floating gate by hot electron. Other electron injection methods include Fowler-Nordheim (FN) tunneling injection and hot-electron injection in an N-channel MOS transistor. In both methods, however, a control gate voltage needs to be increased as compared to a P-channel non-volatile semiconductor element. That is, the P-channel non-volatile semiconductor element is superior in that writing can be performed with a low control gate voltage. A low control gate voltage means that a small electric field is applied to a gate oxide film, and hence the P-channel non-volatile semiconductor element is also superior in the reliability of the gate oxide film.
However, the P-channel non-volatile semiconductor element has a problem in that an optimum value of the control gate voltage for writing varies depending on a threshold voltage of the element.
The optimum value of the control gate voltage for writing varies depending on the threshold voltage of the transistor since the writing is performed by drain-avalanche hot electrons (DAHEs). DAHEs are generated when the transistor is in a saturated state, that is, when the channel pinches off. More DAHEs are generated as the position of the pinch-off point is farther from a drain end. That is, the conditions where more DAHEs are generated are that (1) an absolute value of a voltage between the drain and the source is large and that (2) a difference between an absolute value of a voltage between the control gate and the source and an absolute value of the threshold voltage as seen from the control gate is larger than 0 and is close to 0. The optimum value of the control gate voltage for writing varies depending on the threshold voltage of the transistor because of the condition (2).
Controlling the control gate voltage in accordance with the threshold voltage needs a circuit for controlling the control gate voltage and a circuit for monitoring the threshold voltage, which leads to an increase in size of peripheral circuits and is not preferred. Setting a high drain voltage cancels the above-mentioned advantage that the control gate voltage for writing can be set low, which is again not preferred.
From the above, there is a problem in that, if the control gate voltage for writing deviates from an optimum value, the write amount may become insufficient to cause a write failure. Even when the control gate voltage has a value optimum for writing, the threshold voltage as seen from the control gate varies by electron injection into the floating gate for writing. That is, the control gate voltage deviates from the optimum value for writing, and hence sufficient writing may not be performed. Also in the case where an erase operation of removing electrons from the control gate is insufficient or excessive, the control gate voltage deviates from the optimum value for writing, and hence sufficient writing may not be performed.